In a 90-nm-node semiconductor device, to form an active layer or a Cu wiring, a trench pattern having a narrow pitch of 100 nm or less may need to be formed. However, even if a high-cost exposure apparatus using a short-wavelength light source having a wavelength of 193 nm or less is used, a minimum pitch pmin of a pattern which can be formed in an exposure process may be restricted to pmin=λ/NA (here, λ denotes a wavelength and NA denotes a numerical aperture). For example, when an exposure process is performed using an exposure apparatus having a wavelength of 248 nm and a NA of 0.68, a realizable minimum pitch pmin may be restricted to 365 nm.
To address such a problem, a double exposure method of performing an exposure process using double masks to form a photoresist (PR) pattern may be used. The double exposure method may be used to reduce a pattern pitch of a semiconductor device. The double exposure method may be performed using two masks to form a final pattern and may improve a resolution of a photoresist pattern finally manufactured. Because the PR pattern functions as an etching hard mask if a deep narrow pattern is formed in a reactive ion etching (RIE) process, the pitch of a pattern which can be realized when a narrow trench pattern having a pitch of 100 nm or less may be formed in the etching process, may be restricted.